1. Technical Field
The present invention relates to a test apparatus and a test method.
2. Related Art
A test apparatus of a semiconductor memory such as DRAM and SRAM writes data to a memory under test, and reads the written data from the memory under test. The test apparatus then compares the read data with an expected value, for detecting a failed cell of the memory under test.
Recent years have seen growing attention to the problem of power consumption increase of these memories as they have a higher speed and a larger capacity. Semiconductor memories operable to switch whether to receive bit inverted addresses and receive non-bit inverted addresses appear on the market in response to this trend. A controller accessing this type of semiconductor memory can provide it with addresses with less change in bits. Accordingly, this type of semiconductor memory can have reduced power consumption inherent in address processing can be reduced with.
The test apparatus writes data to or read data from a predetermined address of a memory under test, by executing a test program created in advance. Therefore, when testing such a semiconductor memory, it has been necessary to create the test program taking into consideration whether the address should undergo bit inversion or not in advance. This makes creation of the test program for testing semiconductor memories difficult and troublesome.